Semiconductor device and semiconductor assembly apparatus for semiconductor device

ABSTRACT

In a semiconductor device, a plurality of linear semiconductors of a predetermined length, on which electronic element are formed, are aligned laterally and in parallel. A semiconductor assembly apparatus for assembling the semiconductor device, aligns the linear semiconductors in parallel via an arranging member. The linear semiconductors are interconnected by a connecting member in the semiconductor assembly apparatus.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and asemiconductor assembly apparatus for assembling the semiconductordevice.

[0003] 2. Description of the Related Art

[0004] In conventional semiconductor devices, circuits are formed on aflat silicon wafer. In order to decrease manufacturing expense, a largediameter single silicon crystal column is manufactured through a crystalgrowth method, which is then divided into a multitude of wafers. Themanufacturing apparatus becomes more expensive as the diameter of thesingle crystal column increases. During manufacture of the conventionalsemiconductor device, the wafer is conveyed by a belt conveyer, forexample, through many manufacturing stages, while being subjected tosuccessive manufacturing processes. The manufacturing process isintermittent, taking several months to completion. In response to anincreasing speed in circuit density of 4 times per three years, thefine-process becomes finer and finer. An immense experiment cost forparticle treatment, stepper, CMP and so forth.

SUMMARY OF THE INVENTION

[0005] Therefore, an object of the present invention is to provide alinear semiconductor device and continuous-process semiconductormanufacturing apparatus that has a low manufacturing cost and a shortmanufacturing time.

[0006] Further an object of the present invention is to provide athree-dimensional semi-conductor of high integration without arequirement of forming fine circuitry.

[0007] A semiconductor device according to the present inventionincludes a plurality of linear semiconductors of a predetermined lengthparallelly aligned in a lateral direction, each of which includes alinear semiconductor material and at least one circuit element formed ona surface of the linear semiconductor material.

[0008] A semiconductor device according to the present inventionincludes a plurality of linear semiconductors aligned laterally in asquare matrix or in a 60 degrees rhombic matrix.

[0009] A semiconductor device according to the present inventionincludes a plurality of linear semiconductors electrically connectedwith each other. Projection electrodes are formed on outer surfaces oflinear semiconductors for connecting a plurality of linearsemiconductors with one another and/or fixing the linear semi-conductorsrelative to one another.

[0010] A semiconductor device assembly apparatus according to thepresent invention assembles a semiconductor device utilizing a pluralityof linear semiconductors of a predetermined length. The semiconductorassembly apparatus includes an arranging members for aligning parallellythe linear semiconductors extending in a longitudinal direction, and aconnecting member for connecting the linear semiconductors electricallywith each other.

[0011] A semiconductor device assembly apparatus according to thepresent invention aligns a plurality of linear semiconductors laterallyin a square matrix or in a 60 degrees rhombic matrix.

[0012] In the semiconductor device assembly apparatus according to thepresent invention, preferably the arranging member includes apositioning member for fixing a position of each of the linearsemiconductors relative to the others. Preferably, the connectingmembers electrically connect the linear semiconductors with each otherwhen heated, and the arranging member is liquefied when heated.Preferably, the arranging member includes a plurality of longitudinalmembers of a rhomboid cross-section parallelly aligned in a lateraldirection, each of which decreases in thickness outwardly in the lateraldirection and connected with a neighboring longitudinal member at anarrow connecting portion thereof. Side surface of the longitudinalmembers touch the outer surface of the linear semiconductors.

[0013] The narrow connecting portion in the semiconductor assemblyapparatus may be provided with holes which receive the projectionelectrodes formed on the outer surface of the linear semiconductor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be better understood from thedescription of the preferred embodiments of the invention set forthbelow together with the accompanying drawings, in which:

[0015]FIG. 1 is a partially-sectioned perspective view showing asemiconductor device manufactured by an embodiment of a semiconductorassembly apparatus according to the present invention;

[0016]FIG. 2 is a block diagram showing a manufacturing process formanufacturing the semiconductor device in FIG. 1;

[0017]FIG. 3 is a cross-sectioned elevational view of a semiconductormaterial manufacturing apparatus in FIG. 2;

[0018]FIG. 4 is a block diagram showing a semiconductor circuit formingapparatus in FIG. 2;

[0019]FIG. 5 is a block diagram showing a semiconductor assemblyapparatus in FIG. 2;

[0020]FIG. 6 is a partially sectional view showing a plurality of linearsemiconductors connected by means of connection units and a spacer unit;

[0021]FIG. 7 is a perspective view of the spacer unit in FIG. 6;

[0022]FIG. 8 is a sectional view showing an arrangement of linearsemiconductors of a second embodiment of the semiconductor device;

[0023]FIG. 9 is a sectional view showing a cross-section of the linearsemiconductor material;

[0024]FIG. 10 is a sectional view showing another cross-section of thelinear semiconductor material;

[0025]FIG. 11 is a sectioned elevational view showing a third embodimentof the semiconductor device; and

[0026]FIG. 12 is a sectional view along a line II-II in FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the preferred embodiments of the present inventionare described with reference to the attached drawings.

[0028]FIG. 1 is a perspective view showing a semiconductor device, beinga memory device, manufactured by an embodiment of a semiconductorassembly apparatus according to the present invention. The semiconductordevice 40 includes a plurality of linear semiconductors 50 which arebundled within a rectangular parallelepiped casing 42. A circuit patternis formed on a surface of the linear semiconductors 50 by an embodimentof a circuit forming apparatus according to the present invention. Amulti-layer construction of a plurality of thin semiconductor layers(not shown) including P-type or n-type circuitry elements is formed oneach linear semiconductor 50. The circuitry elements are insulated byinsulator layers and connected through conductor layers. Further,capacitors (not shown) are formed for accumulating charge. A pluralityof input/output terminals 44 are disposed on an outer surface of thecasing 42, and are connected to the linear semiconductors 50.

[0029] Each of the linear semiconductors 50 has a circular cross-sectionwith a diameter of 260 μm and a length of 105 mm. A rectangular bundleof the linear semiconductors 50 is formed, in which 250 linearsemiconductors 50 are aligned horizontally as well as vertically forminga matrix cross-section arrangement. On each linear semiconductor 50,1024 memory devices are aligned in a circumferential direction and131072 memory devices are aligned in an axial direction on the surfaceof each linear semiconductor 50, according to a 0.1 μm rule. One linearsemiconductor 50 has a memory capacity of 16 Mbyte, and thesemiconductor device 40 comprises a total memory capacity of 1 Tbyte.Electrodes 52 are formed on each of the linear semiconductors 50 forconnecting the linear semiconductors 50 with each other.

[0030]FIG. 2 is a block diagram showing a manufacturing process of theembodiment of a semiconductor assembly apparatus, for manufacturing thesemiconductor device 40. First, a linear semiconductor base filament(reference 31 in FIG. 3) is manufactured by a semiconductor materialmanufacturing apparatus 10, and is conveyed to a circuit formingapparatus 100 by a conveyer unit 300. A circuit pattern is formed on asurface of the linear semiconductor base filament (31) in the circuitforming apparatus 100, creating a linear semiconductor material(reference 30 in FIG. 4), from which the linear semiconductor 50 isobtained. The linear semiconductors 50 are conveyed to a semiconductorassembly apparatus 200 by the conveyer apparatus 300, which manufacturesthe semiconductor device 40 in FIG. 1.

[0031]FIG. 3 is a cross-sectioned elevational view of the semiconductormaterial manufacturing apparatus 10 in FIG. 2. The semiconductormaterial manufacturing apparatus 10 includes a double crucible 14 formelting a polycrystalline silicon 11. A supplier 12 is disposed higherthan the double crucible 14 for supplying, via gravity-feeding, thepolycrystalline silicon 11 to the double crucible 14. The doublecrucible 14 includes a cylindrical central furnace 15, and an annularfurnace 17 concentric with and surrounding the central furnace 15. Thecentral furnace 15 and the annular furnace 17 are partitioned by apartition wall 18 and discharge via a common outlet 20 openingdownwardly. The annular furnace 17 has an outer wall 16. The doublecrucible 14 is made of a high purity graphite or quartz. The commonoutlet 20 has a conical wall funneling to a circular bottom exit hole of1 mm diameter, such that the molten silicon MS is extruded into a thinlinear semiconductor base filament 31. The diameter of the circular holeis adjusted in response to a required diameter of the linearsemiconductor base filament 31.

[0032] The polycrystalline silicon 11 is fed into the annular furnace17, and heated until molten at about 1500° C., by an annularelectromagnetic coil 24 concentric with and surrounding the doublecrucible 14, through high frequency heating. The annular electromagneticcoil 24 may be a resistance-type heater, such as a graphite heater.Through-holes 18 a are disposed in the partition wall 18 through whichthe molten silicon MS passes between the central furnace 15 and theannular furnace 17. An annular electromagnet 26, concentric with thedouble crucible 14 and the electromagnetic coil 24, is disposedsurrounding the electromagnetic coil 24, and controls convection of themolten silicon MS. The double crucible 14 is supported by a support body22 made of heat-resisting graphite. The molten silicon MS flows downwardfrom the outlet 20 and is gradually cooled. A plurality of heaters 28 a,28 b and 28 c are aligned along a flowing path of the molten silicon MS,heating temperatures of which are set in a decreasing order. Thus, themolten silicon MS is gradually solidified, such that a linearsemiconductor base filament 31 of single silicon crystal is formed.

[0033] A temperature gradation of the heaters 28 a, 28 b and 28 c isadjusted in response to the set diameter of the outlet 20. Theelectromagnet 26 and the heaters 28 a, 28 b and 28 c are controlled by acontrol apparatus (not shown). The double crucible 14 and heaters 28 ato 28 c are encapsulated by a heat insulated housing 32. The cooledlinear semiconductor base filament 31 exits through a bottom opening 32a and is coiled on a drum (not shown in FIG. 3, reference 102 in FIG.4). The linear semiconductor base filament 31, in this embodiment, has adiameter of 260 μm.

[0034] Due to surface tension, a cross-section of the molten silicon MSbecomes circular. The diameter of the linear semiconductor base filament31 of the silicon single crystal is controlled by the diameter of theoutlet 20 and the cooling by the heaters 28 a, 28 b and 28 c. The moltensilicon MS is cooled from the outer surface, and crystal defects arecompressed by the solidifying pressure, separating out to the outersurface. The crystal defects are removed by a removing apparatus (notshown), such as an acid processing apparatus.

[0035] A pressure and heat application unit (not shown) may be furtherdisposed for improving the single crystal of the linear semiconductorbase filament 31, which is manufactured by the double crucible 14. Thelinear semiconductor base filament 31 that extends vertically anddownwardly from the outlet opening 32 a is axially pulled by two pairsof rollers (not shown). The linear semiconductor base filament 31,undergoes heat treatment at a temperature enabling recrystallization,such that silicon not crystallized by the heaters 28 a, 28 b and 28 c iscrystallized to a single crystal.

[0036] The linear semiconductor base filament 31 is coiled on the supplydrum 102 (FIG. 4) and supplied by the conveyer apparatus 300 to thesemiconductor circuit forming apparatus 100 (FIG. 2).

[0037]FIG. 4 is a generic block diagram showing the embodiment of thecircuit forming apparatus. The semiconductor circuit forming apparatus100 includes a supply drum 102 and a coiling drum 104 driven by firstand second drivers 103 and 105, respectively. An oxide layer has beenalready coated on the outer surface of the linear semiconductor basefilament 31, and the oxide layer is coated over with a nitride layer.The linear semiconductor base filament 31 is wound off the supply drum102 and supplied to the semiconductor circuit forming apparatus 100. Thecircuit pattern is formed on the linear semiconductor base filament 31,generating a linear semiconductor material 30, and the linearsemiconductor material 30 is taken up by the coiling drum 104. Thedrivers 103 and 105 are controlled by a control apparatus 107.

[0038] In the semiconductor circuit forming apparatus 100, “k” (k:integer number) number of circuit patterns are formed by repeating thecircuit pattern forming process “k” times, using a resist layer and ascan beam for drawing a circuit pattern on the resist layer. “k” circuitpattern forming apparatuses 110 to 130 (only three are shown for ease ofunderstanding) are aligned along a conveyer path of the linearsemiconductor base filament 31.

[0039] In the first circuit pattern forming apparatus 110, a gate oxidelayer is formed, in the second circuit pattern forming apparatus 120 andin the following circuit pattern forming apparatuses, sources, drains,insulating layers and conductor layers are formed in the P-type orn-type semiconductor layers.

[0040] Next, the first circuit pattern forming apparatus 110 isdescribed. The first circuit pattern forming apparatus 110 includes aresist layer forming portion 112, a drawing portion 114, an etchingportion 116 and a post-process portion 118, in this order from thesupply drum 102.

[0041] The second and the third circuit pattern forming apparatuses 120and 130 are similar to the first circuit pattern forming apparatus 110,and corresponding components are designated by increasing likereferences by “10” and by “20”, respectively.

[0042] The linear semiconductor base filament 31 is coated by the oxidelayer, and the oxide layer is coated by the nitride layer, prior to thefirst pattern forming process by the first pattern forming apparatus110.

[0043] In the resist layer forming portion 112, a liquid photoresist isapplied to the linear semiconductor base filament 31, and is thermallydried. Thus, the resist layer is formed S as a protective layer againstthe etching. Since well-known conventional methods are used for theresist layer forming and thermal drying, descriptions are omitted.

[0044] In the graphic portion 114, the liner semiconductor base filament31 coated with the photo-resist (called “linear semiconductor material30”, hereinafter) is exposed to an electron beam and then developed. Theresist layer selectively remains without being etched.

[0045] In the etching portion 116, an acid etching liquid is blownagainst the linear semiconductor material 30 to remove an exposednitride layer, allowing the first thin nitride layer corresponding tothe first circuit pattern to be formed. Next, a channel-stopper isformed by ion-shooting and so forth, then the resist layer is removed.Since a conventionally well-known method is applied for the etching andresist layer removal, descriptions are omitted.

[0046] In the post-processing portion 118, a field oxidation process, anitride layer etching process, an oxide layer etching process, agate-oxidation process and a polysilicon build-up process are performed.Since these processes are well-known, descriptions are omitted.

[0047] The linear semiconductor material 30 on which the first thinlayer of the first circuit pattern is formed, is transferred to thesecond circuit pattern forming apparatus 120, such that the secondcircuit pattern is additionally formed. The circuit pattern forming isrepeated “k” times and the total layers of the circuit patterns aresuccessively formed. When the total layers are formed and the linearsemiconductor material 30 is coiled on the coiling drum 104, the linearsemiconductor material 30 is sectioned into predetermined lengthsforming linear semiconductors 50.

[0048] Different processes are performed in the post-processing portions118, 128 and 138 in the circuit pattern forming apparatuses 110, 120 and130, respectively. For example, a source-drain forming process and aphosphorous-glass (“PSG”, hereinafter) build-up process are performed inthe second post-process portion 128. An aluminum deposition process isperformed in the third post-process portion 138.

[0049] In the etching portion (116, 126, 136) of each circuit patternforming apparatus (110, 120, 130), an outermost layer of the linearsemiconductor material 30 which is formed in the previous apparatus isetched. In the post-processing portion 118 of the first circuit patternforming apparatus 110, for example, a polysilicon layer is formed as theoutermost layer on which a second layer is etched according to thesecond circuit pattern in the etching portion 126 of the next circuitpattern forming apparatus 120.

[0050] Similarly, in the post-processing portion 128 of the secondcircuit pattern forming apparatus 120, a PSG layer is formed as theoutermost layer on which a third layer is etched according to the thirdcircuit pattern in the etching portion 136 of the circuit patternforming apparatus 130. An aluminum layer formed as an outermost layer onthe linear semiconductor material 30 in the post-processing portion 138,is etched by an etching portion (not shown) according to a fourthcircuit pattern in a fourth circuit pattern forming apparatus (notshown).

[0051] The linear semiconductor material 30 is coiled on the coilingdrum 104, and is transferred to the semiconductor assembly apparatus 200by the conveyer apparatus 300 (FIG. 2).

[0052]FIG. 5 is a generic block diagram showing the semiconductorassembly apparatus in FIG. 4. The semiconductor assembly apparatus 200includes a projection electrode forming apparatus 210, a shearingapparatus 220, a connecting apparatus 230 and an assembling apparatus240.

[0053] In the projection electrode forming apparatus 210, the projectionelectrodes 52 are formed on the outer surface of the linearsemiconductor 50. A metal material is disclosed in portions of the outersurface where the projection electrodes 52 are to be formed, while otherportions remain coated with the oxide layer. A metal layer is built-upon the disclosed metal and a plating is applied, thus the projectionelectrodes 52 are formed. A metal-bump is transferred to the outersurface of the linear semiconductor 50 under a pressure and a heat.

[0054] In the shearing apparatus 220, the linear semiconductor 50 isseparated into desired lengths, for example, 105 mm.

[0055] In the connecting apparatus 230, 62500 of the linearsemiconductors 50 are aligned and bundled into a matrix cross-sectionconfiguration of 250×250. Neighboring pairs of the linear semiconductors50 are contacted and electrically connected at their projectionelectrodes 52. In FIG. 6, longitudinal central axes 50 a of the linearsemiconductors 50 are aligned along horizontal parallel lines M andalong vertical parallel lines N. A distance between axes 50 a of thelinear semiconductors 50 neighboring in a horizontal or verticaldirection is equal to a diameter of the linear semiconductor 50 plus athickness of a pair of the projection electrodes 52.

[0056] A high-temperature inactive gas of 300° C. is supplied intospaces between the linear semiconductors 50 such that the projectionelectrodes 52 become molten and fuse, allowing an electrical connectionto occur between adjacent projection electrodes 52. The spacer unit 232is liquefied at a temperature lower than the melting temperature of theprojection electrodes 52. The spacer unit 232 is made of acrylic resin,polyethylene or other material which does not deteriorate the linearsemiconductors 50 upon melting.

[0057] In the assembling apparatus 240 (FIG. 5), 62500 of the linearsemiconductors 50 are incorporated in the casing 42, and predeterminedlinear semiconductors 50 are electrically connected to the outerterminals 44. Through the processes above, the semiconductor device 40in FIG. 1 is obtained.

[0058] The projection electrode forming apparatus 210 may be positionedprior to the coiling drum 104 in the semiconductor circuit formingapparatus 100. The order of the processes in the projection electrodeforming apparatus 210 and the shearing apparatus 230 may be reversed ifnecessary.

[0059]FIG. 7 is a perspective view of the spacer unit 232 in FIG. 6.Upon liquefaction, the spacer unit 232 can be washed away by a solventflowing through spaces between the linear semiconductors 50. When thespacer unit 232 is made of acrylic resin, the solvent for removing theliquefied spacer unit 232 is a chlorine-based solvent, such aschloroform, and when made of polyethylene, tetrahydrofuran, for example,is used.

[0060] The spacer unit 232 includes a plurality of longitudinal members234 of a rhomboid cross-section aligned in parallel in a lateraldirection, each of which decreases in thickness outwardly in the lateraldirection. Each longitudinal member 234 is connected with a neighboringlongitudinal member 234 at a narrow portion thereof. The longitudinalmember 234 are uniformly and linearly aligned with a longer diagonal Lof the rhomboids, being contiguous with each other.

[0061] The linear semiconductors 50 contact side surfaces 234 b of thelongitudinal members 234 and are supported by the side surfaces 234 b.At narrow portions 234 a of the longitudinal members 234, a plurality ofholes 236 are formed along an interposed strip 235, interposed betweenthe longitudinal members 234 and joining adjacent narrow portion 234 a.The holes 236 correspond to the projection electrodes 52, such thatlinear semiconductors 50, supported by one spacer unit 232, areaccurately positioned along lines M and N. By thus aligning the linearsemiconductors 50 horizontally and vertically, interposed by the spacerunit 232, a matrix alignment is formed. Each of the longitudinal members232 is surrounded by four linear semiconductors 50 contacting the fourside surfaces 234 b.

[0062] In order to align 250×250 linear semiconductors 50 in the firstembodiment, 249 spacer units 232 are necessary, and 251 longitudinalmembers 234 are necessary in each spacer unit 232. A process of aligning250 linear semiconductors 50 and laying the spacer unit 232 on thelinear semiconductors 50 is repeated 250 times. Thus, 62500 linersemiconductors 50 are unified in a block matrix arrangement.

[0063] The 62500 linear semiconductors 50 are simultaneously welded inthe first embodiment above, however, welding may be performed plane byplane for the 250 linear semiconductors 50.

[0064] As mentioned above, the semiconductor device 40 is constructed bythe linear semiconductors 50 being aligned in a matrix arrangement. Inthe conventional semiconductor manufacturing apparatus, only one surfaceof a wafer is available for forming a circuit pattern, however, in theabove embodiment, all of the circumferential surface of the linearsemiconductor 50 is available for forming the circuit pattern, thus afar greater percentage area is utilized. The semiconductor devicebecomes smaller, when compared with a conventional semiconductor deviceof the same capability, and the process speed is improved due to adecrease in delay time in the smaller semiconductor device.

[0065] Conductor lines may be utilized, being a high speed conductors ofgold, aluminum and so forth, thus a high working speed is obtained.Electrical noise reduction is possible for each of the linearsemiconductors 50, thus a three-dimensional circuit of practically zeronoise is possible. Extremely high density is realized in thesemiconductor device 40, and, for example, a compact DRAM of highcapacity is thus obtainable.

[0066] A large scale manufacturing apparatus is necessary for large sizesingle silicon crystal column of about 200 mm in diameter for aconventional semiconductor device, while the semiconductor base filamentmanufacturing apparatus of the above embodiment handles semiconductorsof not more than 5 mm in diameter, and is much smaller in size than aconventional apparatus. The process speed of the manufacturing becomeshigher than that of a conventional apparatus. The manufacturing cost andmanufacturing time are decreased due to a continuous process, not beingan intermittent process as in the manufacture of a conventional device.

[0067] In a conventional liquid phase epitaxial process, wafers arealigned in a furnace and a silicon solvent is injected, while, in theembodiment above, the linear semiconductor base filament 31 is passedthrough a container of silicon solvent. Thus, the manufacturing processbecomes simpler, and the manufacturing time becomes shorter.

[0068]FIG. 8 is a sectional view showing an arrangement of the linearsemiconductors 50 in a second embodiment of the semiconductor device.The second embodiment is different only in an arrangement manner of thelinear semiconductors 50.

[0069] In FIG. 8, the linear semiconductors 50 are aligned in a 60degrees rhombic matrix, differently from the first embodiment of thesquare matrix. The axes 50 a of the linear semiconductors 50 arepositioned on points of intersection of parallel lines P and Q crossingeach other at angles of 60 degrees.

[0070] In this embodiment, each of the linear semiconductors 50 isspaced from neighboring linear semiconductors 50 by substantially equaldistances, being the diameter of the linear semiconductor 50 plus thethickness of a pair of the projection electrodes 52. Since, in the firstembodiment, distance between neighboring linear semiconductors 50 in adiagonal direction is {square root}{square root over (2)}×d (d: distancebetween horizontal or vertical neighbors), much straighter linearsemiconductors (50) may be incorporated in a semiconductor device (40)of the second embodiment than those of the first embodiment.

[0071]FIGS. 9 and 10 are sectional views showing a cross-section of thelinear semiconductor material 30. FIG. 10 shows a deformation of ovalcross-section due to directional ununiformity of temperature and gasdensity. Various deformations may occur depending on a composition ofthe material, material manufacturing condition, circuit formingcondition, and so forth. The cross-section of the linear semiconductor50 may be deformed to be a polygon or an oval due to an obliquecrystallographic axis or to thermal deformation. The cross-section maybe other polygons, such as a rectangle, a hexagon and so forth, or anoval, a chamfered polygon, a deformed polygon, or other various shapes.The linear semiconductor material 30 of the present invention may have across-section of any the above shapes.

[0072] The semiconductor device 40 according to the present inventionmay include a coolant fluid circulated through spaces between the linearsemiconductors 50 to allow heat-sink cooling. The coolant fluid is aninactive liquid reacting neither with the semiconductors 50 nor with themetal, or an inactive gas, such as argon, or nitrogen. A pressure unitfor feeding coolant may be disposed in a vicinity of the semiconductordevice 40 to feed the coolant fluid to the outer surface of linearsemiconductors 50. The axes 50 a of the linear semiconductors 50 may beinclined from the horizontal, such that the gas coolant flows due toconvection.

[0073]FIG. 11 is a sectioned elevational view showing a third embodimentof the semiconductor device 40, and FIG. 12 is a sectional view along aline II-II in FIG. 11. The semiconductor device 40 includes arectangular parallelepiped sealed casing 42 in which a plurality of thelinear semiconductors 50, of a predetermined length, are aligned inparallel to exhibit a square matrix cross-section perpendicular to alongitudinal direction of the linear semiconductor device 40. The linearsemiconductors 50 are interconnected at projection electrodes 52. Aplurality of outer terminals 44 project from a bottom surface of thecasing 42, and are electrically connected with predetermined linearsemiconductors 50. Neighboring outer terminals 44 are insulated fromeach other an insulated layer 46.

[0074] The casing 42 is filled with a coolant fluid 41 that iscirculated by fan 43, positioned adjacent to an end portion 50 c of thelinear semiconductors 50. The coolant fluid 41 is pure water, nitrogengas or other fluid that does not deteriorate the linear semiconductors50. The fan 43 is connected to and driven by a driver circuit (notshown) formed on the linear semiconductors 50. An axial flow pump may beutilized instead of the fan 43. A temperature of the coolant fluid 41 issensed by a circuit formed on the linear semiconductors 50 such that aquantity of the flowing coolant is controlled.

[0075] The coolant fluid 41 flows through a space 54 between neighboringlinear semiconductors 50 in a direction A parallel to the central axes50 a of the linear semiconductors 50. The linear semiconductors 50 arecooled by the flowing coolant fluid 41. The space 54 is exaggeratedlyenlarged for ease of understanding, and the linear semiconductors 50 arepartially shown in FIG. 12.

[0076] A passageway 45 is formed over the bundle of linearsemiconductors 50 through which the coolant fluid 41 flows in thereverse direction to the flowing direction A in the space 54, from anend portion 50 b of the linear semiconductor 50 opposite the end portion50 c. Then, the coolant fluid 41 is filtered by a filter 47 downstreamof and adjacent to the fan 43, before being fed by the fan 43 to thelinear semiconductors 50 again. Thus, the coolant fluid 41 iscirculated. Since the casing 42 is sealed and the filter 47 is disposedin the passage of the coolant fluid, the coolant fluid 41 is kept clean.

[0077] The casing 42 is made of a material of high heat conductivity,such as a metal or crystallized carbon fiber board. A heat-sink 49 isfixedly adhered to an outer surface of the casing 42, parallel to thepassageway 45, such that heat energy carried by the coolant fluid 41after the cooling of the linear semiconductors 50 is dissipated by thecasing 42 or by the heat-sink 49.

[0078] In the semiconductor device 40 of the third embodiment, an effectis achieved that the semiconductor device 40 is prevented from anadverse temperature rise, in addition to the effect of having a compactsize.

[0079] Similarly to the first embodiment, the manufacturing cost and themanufacturing time are decreased, because the manufacturing apparatusbecomes smaller and the manufacturing process is continuous.

[0080] Finally, it will be understood by those skilled in the art thatthe foregoing description is of preferred embodiments of the device, andthat various changes and modifications may be made to the presentinvention without departing from the spirit and scope thereof.

[0081] The present disclosure relates to subject matters contained inJapanese Patent Application No. 10-194570 (filed on Jul. 9, 1998) whichis expressly incorporated herein, by reference, in its entirety.

1. A semiconductor device comprising: a plurality of linearsemiconductors of a predetermined length that are aligned laterally andin parallel, at least one electronic element being formed on an outersurface of said linear semiconductors.
 2. The semiconductor device ofclaim 1 , wherein ends of said linear semiconductors are aligned in asquare matrix arrangement.
 3. The semiconductor device of claim 1 ,wherein ends of said linear semiconductors are aligned in a 60 degreesrhombic arrangement.
 4. The semiconductor device of claim 1 , whereinsaid linear semiconductors are electrically interconnected.
 5. Thesemiconductor device of claim 1 , wherein each of said linearsemiconductors comprises at least one projection electrode fixed to andelectrically connected with a corresponding projection electrode of anadjacent linear semiconductor.
 6. A semiconductor assembly apparatusthat assembles said semiconductor device of claim 1 , comprising: anarrangement member that aligns said plurality of linear semiconductorslaterally and in parallel; and a connecting member that interconnectssaid linear semiconductors aligned by said arranging member.
 7. Thesemiconductor assembly apparatus of claim 6 , wherein said arrangementmember arranges ends of said linear semiconductors in a square matrixarrangement.
 8. The semiconductor assembly apparatus of claim 6 ,wherein said arrangement member arranges ends of said linearsemiconductors in a 60 degrees rhombic arrangement.
 9. The semiconductorassembly apparatus of claim 6 , wherein said arrangement member includesan alignment member that securely positions said linear semiconductors.10. The semiconductor assembly apparatus of claim 9 , wherein saidconnecting member electrically interconnects said linear semiconductorswhen heated, and said arrangement member is liquefied when heated. 11.The semiconductor assembly apparatus of claim 9 , wherein saidarrangement member includes longitudinal rhomboid cross-section membersand connecting members connecting adjacent longitudinal members.
 12. Thesemiconductor assembly apparatus of claim 11 , wherein side surfaces ofsaid longitudinal members contact said outer surface of said linearsemiconductors.
 13. The semiconductor assembly apparatus of claim 11 ,wherein said connecting member is provided with holes that receive andengage projection electrodes formed on said outer surface of said linearsemiconductors.
 14. The semiconductor device of claim 1 , furthercomprising a coolant fluid that flows adjacent to said linearsemiconductors so as to cooling said liear semiconductors.